MCP3910 datasheet(33/90 Pages) MICROCHIP

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DS20005116D-page 33

MCP3910

5.3.4

DITHER SETTINGS

All modulators include a dithering algorithm that can be

enabled through the DITHER[1:0] bits in the CONFIG0

SFDR (for high OSR settings), while slightly increasing

the noise floor of the ADCs. For power metering appli-

cations and applications that are distortion-sensitive, it

is recommended to keep dither at maximum settings

for best THD and SFDR performance. In the case of

power metering applications, THD and SFDR are

critical specifications. Optimizing SNR (noise floor) is

not problematic due to the large averaging factor at the

output of the ADCs. Therefore, even for low OSR set-

tings, the dithering algorithm will show a positive impact

on the performance of the application.

5.3.5

MODULATOR OUTPUT BLOCK

If the user wishes to use the modulator output of the

device, the appropriate bits to enable the modulator

output must be set in the STATUSCOM register.

When EN_MDAT = 1, the modulator output of the

corresponding channel is present at the corresponding

MDAT output pin as soon as the command is placed.

Additionally, the corresponding SINC filter is disabled in

order to consume less current. The corresponding data

ready pulse is also not present at the DR output pin.

The data ready output pin is then placed in high-

impedance, regardless of the DR_HIZ setting, so that

the user can tie this pin to an external supply or ground

for lower noise behavior. When EN_MDAT = 0, the

corresponding SINC filters are back to normal

operation and the corresponding MDAT outputs are in

high-impedance.

Since the Delta-Sigma modulators have a 5-level output

given by the state of the four comparators with

thermometer coding, their outputs can be represented

on four bits, each bit giving the state of the corresponding

comparator (see Table 5-3). These bits are present on

the MOD register and are updated at the DMCLK rate.

In order to output the comparators’ result on a separate

pin (MDAT0 and MDAT1), these comparator output bits

have been arranged to be serially output at the AMCLK

rate (see Figure 5-2).

This 1-bit serial bitstream is the same as would be

produced by a 1-bit DAC modulator with a sampling

frequency of AMCLK. The modulator can either be

considered as a 5-level output at DMCLK rate or a 1-bit

output at AMCLK rate. These two representations are

interchangeable. The MDAT outputs can therefore be

used in any application that requires 1-bit modulator

outputs. Such applications will often integrate and filter

the 1-bit output with SINC or more complex decimation

filters computed by an MCU or a DSP.

FIGURE 5-2:

MDAT Serial Outputs in

Function of the Modulator Output Code.

Since the Reset and shutdown SPI commands are

asynchronous, the MDAT pins are resynchronized with

DMCLK after each time the part goes out of Reset and

shutdown.

This means that the first output of MDAT, after a Soft

Reset or a shutdown, is always ‘0011’ after the first

DMCLK rising edge.

The two MDAT output pins are high-impedance if the

RESET pin is low and they are also in high-impedance

state during the Two-Wire Interface mode.

TABLE 5-3:

DELTA-SIGMA MODULATOR

CODING

COMP[3:0]

Code

Modulator

Output Code

MDAT Serial

Stream

1111

0111

0011

0001

-1

0001

0000

-2

0000

DMCLK

MDAT+2

MDAT+1

MDAT+0

MDAT-1

MDAT-2

COMP

AMCLK

[3]

COMP

[2]

COMP

[1]

COMP

[0]

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