MCP3910 datasheet(53/90 Pages) MICROCHIP

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DS20005116D-page 53

MCP3910

6.10

Locking/Unlocking Register Map

Write Access

The MCP3910 digital interface includes an advanced

security feature that permits locking or unlocking the

miscommunication that can corrupt the desired config-

uration of the device, especially an SPI read becoming

an SPI write because of the noisy environment.

The last register address of the register map

(0x1F: LOCK/CRC) contains the LOCK[7:0] bits. If

these bits are equal to the password value (which is

equal to the default value of 0xA5), the register map

write access is not locked. Any write can take place and

the communications are not protected.

When the LOCK[7:0] bits are different than 0xA5, the

and therefore, the full device configuration, is write-

protected. Any write to an address other than 0x1F will

yield no result. All the register addresses, except for

0x1F, become read-only. In this case, if the user wants

to change the configuration, the LOCK[7:0] bits have to

be reprogrammed back to 0xA5 before sending the

desired WRITE command.

The LOCK[7:0] bits are located in the last register so that

the user can program the whole register map, starting

from 0x09 to 0x1E within one continuous write sequence,

and then lock the configuration at the end of the sequence

with writing all zeros, for example, in the 0x1F address.

6.11

Detecting Configuration Change

through CRC-16 Checksum on

Interrupt Flag

In order to prevent internal corruption of the register and

to provide additional security on the register map config-

uration, the MCP3910 device includes an automatic and

continuous CRC checksum calculation on the full regis-

ter map Configuration bits. This calculation is not the

same as the communication CRC checksum described

in Section 6.9 “Securing Read Communications

Through CRC-16 Checksum”

. This calculation takes

the full register map as the CRC message and outputs a

checksum on the CRCREG[15:0] bits located in the

LOCK/CRC register (address: 0x1F).

Since this feature is intended to protect the configuration

of the device, this calculation is run continuously only

when the register map is locked (LOCK[7:0] is different

from 0xA5, see Section 6.10 “Locking/Unlocking

). If the register map is

unlocked, the CRCREG[15:0] bits are cleared and no

CRC is calculated.

The calculation is fully completed in 12 DMCLK periods

and refreshed every 12 DMCLK periods continuously.

The CRCREG[15:0] bits are reset when a POR or a

Hard Reset occurs. All the bits contained in the defined

registers, from addresses 0x09 to 0x1F, are processed

by the CRC engine to give the CRCREG[15:0] bits. The

DRSTATUS[5:0] bits are set to ‘1’ (default) and the

CRCREG[15:0] bits are set to ‘0’ (default) for this

calculation engine, as they could vary during the

calculation.

An interrupt flag can be enabled through the EN_INTCRC

bit in the STATUSCOM register and provided on the DR

pin when the configuration has changed without a

WRITE

command being processed. This interrupt is a

logic low state. This interrupt is cleared when the

processed anymore).

At power-up, the interrupt is not present and the register

map is unlocked. As soon as the user finishes writing its

configuration, the user needs to lock the register map

(writing 0x00, for example, in the LOCK bits) to be able

to use the interrupt flag. The CRCREG[15:0] bits will be

calculated for the first time in 12 DMCLK periods. This

first value will then be the reference checksum value and

will be latched internally, until a Hard Reset, a POR or an

unlocking

the

map

happens.

The

CRCREG[15:0] bits will then be calculated continuously

and checked against the reference checksum. If the

CRCREG[15:0] bits are different than the reference, the

interrupt sends a flag by setting the DR pin to a logic low

state until it is cleared.

6.12

Interface Mode Selection

(SPI or Two-Wire)

The MCP3910 includes two different digital interfaces:

a standard four-wire half-duplex SPI interface (see

Section 6.0 “SPI Serial Interface Description”

) and

a two-wire interface dedicated for digitally isolated

applications (see Section 7.0 “Two-Wire Serial

Interface Description”

The selection between these two interfaces is possible

only when the CLKEXT bit is logic high (CLKEXT = 1).

This is the case by default at POR. When the

CLKEXT = 1 condition is true, the OSC2/MODE pin

becomes the selection input pin for the Interface mode.

When

OSC2/MODE

logic

low

during

the

CLKEXT = 1 condition, the SPI Interface is selected.

When OSC2/MODE pin is logic high, the Two-Wire

Interface mode is selected (see Figure 1-5 for the

Two-Wire Interface mode selection timing diagram).

If the OSC2/MODE pin is left floating while CLKEXT = 1,

an internal pull-down (35 µA typical current) automatically

selects the SPI mode as the default interface.

The MODE selection is not combinatorial, it is latched

at each POR, Hard Reset and Watchdog Time Reset.

In other words, to change from one interface mode to

another, the user needs to create one of these three

Resets and change the OSC2/MODE logic input state

before exiting the applied Reset.

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