MCP3910 datasheet(67/90 Pages) MICROCHIP

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DS20005116D-page 67

MCP3910

9.1

CHANNEL Registers –

ADC Channel Data

Output Registers

The ADC Channel Data Output registers always

contain the most recent A/D conversion data for each

channel. These registers are read-only. They can be

accessed independently or linked together (with the

READ[1:0] bits). These registers are latched when an

ADC read communication occurs. When a data ready

event occurs during a read communication, the most

current ADC data are also latched to avoid data

corruption issues. These registers are updated and

latched together if DR_LINK = 1, synchronously with

the data ready pulse (toggling on the most lagging

ADC channel data ready event).

Name

Bits

Address

Cof

CHANNEL0

0x00

CHANNEL1

0x01

MCP3910 CHANNEL DATA OUTPUT REGISTERS

R-0

DATA_CHn[23:16]

bit 23

bit 16

R-0

DATA_CHn[15:8]

bit 15

bit 8

R-0

DATA_CHn[7:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-0

DATA_CHn[23:0]:

Output Code from ADC Channel n bits

These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. These data can

be formatted in 16-/24-/32-bit modes, depending on the WIDTH_DATA[1:0] settings (see Section 5.5

“ADC Output Coding”

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