CS4525 datasheet(64/98 Pages) CIRRUS

64 / 98 page

DS726PP1

CS4525

6.8

I²C Control Port Description and Timing

The control port is used to access the registers allowing the CS4525 to be configured for the desired oper-

ational modes and formats. The operation of the control port may be completely asynchronous with respect

to the audio sample serial port. However, to avoid potential interference problems, the control port pins

should remain static if no operation is required. The control port operates in I²C Mode, with the CS4525 act-

ing as a slave device.

SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 k

Ω pull-up

or pull-down on the AUX_LRCK/AD0 pin will set AD0, the least significant bit of the device address. A pull-

up to VD will set AD0 to ‘1’ and a pull-down to DGND will set AD0 to ‘0’. The state of AUX_LRCK/AD0 is

sensed, and AD0 is set upon the release of RESET.

The signal timings for a read and write cycle are shown in Figure 33 and Figure 34. A Start condition is de-

fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the

clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4525 after

a Start condition consists of a 7 bit device address field and a R/W bit (high for a read, low for a write). The

upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS4525, the device ad-

dress field, which is the first byte sent to the CS4525, should match 100101 followed by the setting of AD0.

The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the memory address

pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the

or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from

the CS4525 after each input byte is read, and is input to the CS4525 from the microcontroller after each

transmitted byte.

Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown

in Figure 34, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-

dition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 100101x0 (device address and write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write. (Optional.)

Send start condition.

Send 100101x1(device address and read operation).

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 0 1 0

AD0

SDA

INCR

5 4

3 2 1 0

1 0

7 6

1 0

16 17 18 19

10 11

13 14 15

27 28

DATA +n

Figure 33. Control Port Timing, I²C Write

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 0

1 0 1 AD0 0

SDA

0 1 AD0 1

CHIP ADDRESS (READ)

START

INCR

3 2

1 0

12 13 14 15

20 21 22 23 24

26 27 28

10 11

17 18 19

ACK

DATA + n

STOP

Figure 34. Control Port Timing, I²C Read

CS4525 Datenblatt(PDF) 64 Page - Cirrus Logic

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