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CS4525 Datenblatt(PDF) 37 Page - Cirrus Logic

Teilenummer CS4525
Bauteilbeschribung  30 W Digital Audio Amplifier with Integrated ADC
PDF  98 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4525 Datenblatt(HTML) 37 Page - Cirrus Logic

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37
CS4525
6.1.4.10 Peak Signal Limiter
When enabled, the limiter monitors the digital output following the volume control block, detects when
peak levels exceed a selectable maximum threshold level and lowers the volume at a programmable at-
tack rate until the signal peaks fall below the maximum threshold. When the signal level falls below a se-
lectable minimum threshold, the volume returns to its original level (as determined by the individual and
master volume control registers) at a programmable release rate. Attack and release rates are affected
by the soft ramp/zero cross settings and sample rate, Fs.
Recommended settings: Best limiting performance may be realized with the fastest attack and slowest
release setting with soft ramp enabled in the control registers. Use the “minimum” bits to set a threshold
slightly below the maximum threshold to cushion the sound as the limiter attacks and releases.
By default, the limiter affects all channels when the maximum threshold is exceeded on any single chan-
nel. This default functionality is designed to keep all output channels at the same volume level while the
limiter is in use. This behavior can be disabled by clearing the LimitAll bit in the Limiter Cfg 1 register.
Max[2:0]
Output
(after Limiter)
Input
RRate[5:0]
ARate[5:0]
Volume
Limiter
Min[2:0]
Attack/Release Sound
Cushion
Attack/Release Sound
Cushion
Figure 17. Peak Signal Detection & Limiting



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