Preliminary Technical Data

ADIS16209

Rev. PrA | Page 5 of 16

TIMING SPECIFICATIONS

Table 2.

Parameter

Description

Typ

Max

Unit

0.01

2.5

MHz

0.01

1.0

MHz

40

μs

100

μs

Chip select to clock edge

48.8

ns

Data output valid after SCLK edge

100

ns

Data input setup time before SCLK rising edge

24.4

ns

Data input hold time after SCLK rising edge

48.8

ns

Data output fall time

5

12.5

ns

Data output rise time

5

12.5

ns

CS high after SCLK edge

5

ns

TIMING DIAGRAMS

CS

SCLK

Figure 2. SPI Chip Select Timing

CS

SCLK

DOUT

DIN

1

2

3

4

5

6

15

16

W/R

A5

A4

A3

A2

D2

MSB

DB14

D1

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

CS

SCLK

DIN

W/R

A5

A4

A3

A2

A1

A0

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

DATA FRAME

WRITE = 1

READ = 0

REGISTER ADDRESS

DATA FOR WRITE COMMANDS

DON’T CARE FOR READ COMMANDS

Figure 4. DIN Bit Sequence