Preliminary Technical Data

ADIS16209

Rev. PrA | Page 11 of 16

BASIC OPERATION

The ADIS16209 requires only power/ground and SPI

connections. The SPI is simple to hook up and is supported by

many common digital hardware platforms. Figure 21 provides a

simple hook-up diagram, while Table 2, Figure 2, Figure 3

provide timing and bit assignments. Figure 4 provides the bit

sequence for accessing the register memory structure. Each

function within the ADIS16209 has its own register, which has a

unique, 6-bit address. Note that all 16 SCLK cycles are required

for the DIN bit sequence to configure the output for the next

data frame. The ADIS16209 supports full duplex mode

operation. Table 6 provides the entire user register map for the

ADIS16209. For each register, the lower byte’s address is given.

For those registers that have two bytes, the upper byte’s address

is simply the lower byte’s address, incremented by 0x01.

ADIS16209

EMBEDDED

PROCESSOR/

DSP/FPGA

PF

SCK

MOSI

MISO

CS

SCLK

DIN

DOUT

Figure 21. Typical SPI Hook-up

Many of the configuration registers have also been assigned

mirror locations in the flash memory, which effectively provides

them with a backup storage function. To assure the backup of

these registers, the COMMAND register provides an initiation

bit for manual flash updates. The ENDURANCE register

provides a running count of these events.

Table 6. User Register Map

Name

R/W

Flash Backup

Address

Size (Bytes)

Function

Reference

ENDURANCE

R

Yes

0x00

2

Diagnostics, flash write counter (16-bit binary)

SUPPLY_OUT

R

No

0x02

2

Output, power supply

Table 7

XACCL_OUT

R

No

0x04

2

Output, X-axis acceleration

Table 7

YACCL_OUT

R

No

0x06

2

Output, Y-axis acceleration

Table 7

AUX_ADC

R

No

0x08

2

Output, auxiliary ADC

Table 7

TEMP_OUT

R

No

0x0A

2

Output, temperature

Table 7

XINCL_OUT

R

No

0x0C

2

Output, ±90° X-axis inclination

Table 7

YINCL_OUT

R

No

0x0E

2

Output, ±90° Y-axis inclination

Table 7

ROT_OUT

R

No

0x10

2

Output, ±180° vertical rotational position

Table 7

XACCL_NULL

R/W

Yes

0x12

2

Calibration, X-Axis acceleration offset null

Table 16

YACCL_NULL

R/W

Yes

0x14

2

Calibration, Y-axis acceleration offset null

Table 16

XINCL_NULL

R/W

Yes

0x16

2

Calibration, X-axis inclination offset null

Table 17

YINCL_NULL

R/W

Yes

0x18

2

Calibration, Y-axis inclination offset null

Table 17

ROT_NULL

R/W

Yes

0x1A

2

Calibration, vertical rotation offset null

Table 17

0x1C to 0x1F

4

Reserved, do not write to these locations

ALM_MAG1

R/W

Yes

0x20

2

Alarm 1, amplitude threshold

Table 18

ALM_MAG2

R/W

Yes

0x22

2

Alarm 2, amplitude threshold

Table 18

ALM_SMPL1

R/W

Yes

0x24

2

Alarm 1, sample period

Table 19

ALM_SMPL2

R/W

Yes

0x26

2

Alarm 2, sample period

Table 19

ALM_CTRL

R/W

Yes

0x28

2

Alarm, source control register

Table 20

No

0x2A to 0x2F

6

Reserved

AUX_DAC

R/W

No

0x30

2

Auxiliary DAC data

Table 14

GPIO_CTRL

R/W

No

0x32

2

Operation, digital I/O configuration and data

Table 13

MSC_CTRL

R/W

No

0x34

2

Operation, data-ready and self-test control

Table 12

SMPL_PRD

R/W

Yes

0x36

2

Operation, sample rate configuration

Table 8

AVG_CNT

R/W

Yes

0x38

2

Operation, filter configuration

Table 10

SLP_CNT

W

Yes

0x3A

2

Operation, sleep mode control

Table 9

STATUS

R

No

0x3C

2

Diagnostics, system status register

Table 21

COMMAND

W

No

0x3E

2

Operation, system command register

Table 15