ADIS16209

Preliminary Technical Data

Rev. PrA | Page 12 of 16

OUTPUT DATA REGISTERS

Table 7 provides the data configuration for each output data

register in the ADIS16209. Starting with the MSB of the upper

byte, each output data register has the following bit sequence:

new data (ND) flag, error/alarm (EA) flag, followed by 14 data

bits. The data bits are LSB-justified and in the case of the 12-bit

data formats, the remaining 2 bits are not used. The ND flag

indicates that unread data resides in the output data registers.

This flag clears and returns to 0 during an output register read

sequence. It returns to 1 after the next internal sample update

cycle completes. The EA flag indicates an error condition. The

STATUS register contains all of the error flags and provides the

ability to investigate root cause.

Table 7. Output Data Register Formats

Register

Bits

Format

SUPPLY_OUT

12

Binary, +3.3 V = 0x0ABE

1.22 mV

XACCL_OUT

14

Twos complement

0.244 mg

YACCL_OUT

14

Twos complement

0.244 mg

AUX_ADC

12

Binary, +2 V = 0x0CCC

0.6105 mV

TEMP_OUT

12

Binary, +25°C = 0x04FE

−0.47°C

14

Twos complement

0.025°

14

Twos complement

0.025°

14

Twos complement

0.025°

OPERATION CONTROL REGISTERS

Internal Sample Rate

The SMPL_PRD register controls the ADIS16209 internal sample

rate and has two parts: a selectable time base and a multiplier. The

following relationship produces the sample rate:

Table 8. SMPL_PRD Bit Descriptions

Bit

Description

(Default = 0x0001)

15:8

Not used

7

0 = 244.14 μs, 1 = 7.568 ms

6:0

An example calculation of the default sample period follows:

SMPL_PRD = 0x01, B7 − B0 = 00000001

The sample rate setting has a direct impact on the SPI data

rate capability. For sample rates ≥1024 SPS, the SPI SCLK can

run at a rate up to 2.5 MHz. For sample rates <1024 SPS, the SPI

SCLK can run at a rate up to 1 MHz. The sample rate setting

also affects the power dissipation. When the sample rate is set

<1024 SPS, the power dissipation typically reduces by a factor of

68%. The two different modes of operation offer a system-level

trade-off between performance (sample rate, serial transfer rate)

and power dissipation.

Power Management

In addition to offering two different performance modes for

power optimization, the ADIS16209 offers a programmable

shutdown period, which the SLP_CNT register controls.

Table 9. SLP_CNT Bit Descriptions

Bit

Description

(Default = 0x00)

15:8

Not used

7:0

Data bits, 0.5 seconds/code

For example, writing 0x08 to the SLP_CNT register places the

ADIS16209 into sleep mode for 4 seconds. The only way to stop

this process is to remove power or reset the device.

Digital Filtering

The AVG_CNT register controls the moving average digital filter,

which determines the size of the moving average filter, in eight

256). Filter setup requires one simple step: write the appropriate

M factor to the assigned bits in the AVG_CNT register.

Table 10. AVG_CNT Bit Descriptions

Bit

Description

(Default = 0x0004)

15:4

Not used

3:0

Power-of-two step size, maximum binary value = 1000

The following equation offers a frequency response relationship

for this filter:

)

sin(

)

sin(

)

(

S

S

A

t

f

N

t

f

N

f

H

×

×

π

×

×

×

×

π

=

20

0

–20

–40

–60

–80

–100

0.001

0.01

0.1

N = 4

N = 16

N = 128

Figure 22. Frequency Response—Moving Average Filter

Digital I/O Lines

The ADIS16209 provides two, general purpose, digital

input/output lines that have several configuration options.