LP5523 datasheet(19/61 Pages) TI2

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LP5523

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SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017

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7.5 Programming

7.5.1 I2C-Compatible Control Interface

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor

placed somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial

bus data transfer.

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when clock signal is LOW.

Figure 19. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition

is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is

defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates

START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP

condition. During data transmission, the bus master can generate repeated START conditions. First START and

repeated START conditions are equivalent, function-wise.

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP5523 pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP5523 generates an

acknowledge after each byte has been received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). The LP5523 address is defined with ASEL0 and ASEL1

pins, and it is 32h when ASEL1 and ASEL0 are connected to GND. For the eighth bit, a “0” indicates a WRITE

and a “1” indicates a READ. The second byte selects the register to which the data is written. The third byte

contains data to write to the selected register.

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