LP5523 datasheet(20/61 Pages) TI2

20 / 61 page

ack from slave

start

MSB Chip Addr LSB

SCL

ack from slave

MSB Register Addr LSB

MSB

Data

LSB

stop

ack from slave

nack from master

repeated start

data from slave

SDA

start

id =32h

w ack

address = 3Fh

ack

r ack

address 3Fh data

nack

stop

MSB Chip Address LSB

id = 32h

start

MSB Chip Addr LSB

ack

MSB Register Addr LSB

ack

MSB

Data LSB

ack

stop

ack from slave

SCL

SDA

start

id = 32h

ack

addr = 40h

ack

address 40h data

stop

ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C Slave Address (chip address)

LP5523

SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017

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Product Folder Links: LP5523

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Programming (continued)

7.5.1.4 I2C-Compatible Chip Address

ASEL0 and ASEL1 pins configure the chip address for the LP5523 as shown in Table 1.

Table 1. LP5523 Chip Address Configuration

ASEL1

ASEL0

ADDRESS

8-BIT HEX ADDRESS

(HEX)

WRITE/READ

GND

64/65

GND

VEN

66/67

VEN

GND

68/69

VEN

6A/6B

Figure 20. LP5523 Chip Address

This data pattern writes temperature information to the TEMPERATURE WRITE register (40h).

Figure 21. Write Cycle (W = Write; SDA = 0), Id = Chip Address = 32h for LP5523

This data pattern reads temperature information from the TEMPERATURE READ register (3Fh). When a READ

function is to be accomplished, a WRITE function must precede the READ function.

Figure 22. Read Cycle (R = Read; SDA = 1), Id = Chip Address = 32h for LP5523

LP5523 Datenblatt(PDF) 20 Page - Texas Instruments

LP5523 Datenblatt(HTML) 20 Page - Texas Instruments

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