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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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L9663 Datenblatt(PDF) 97 Page - STMicroelectronics |
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L9663 Datenblatt(HTML) 97 Page - STMicroelectronics |
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97 / 106 page  DS11401 Rev 6 97/106 L9663 Electrical characteristics 105 Table 25. SPI communication timing Symbol Parameter / Condition Min Typ Max Unit fSPICLK SCLK frequency - 10 - MHz tCLK-high/low SCLK high/low time 30 - - ns tlead CS to SCLK delay 180 - - ns tlag SCLK to CS delay 45 - - ns tdisablelead SCLK disable lead time 10 - - ns tdisablelag SCLK disable lag time 10 - - ns tMOSI-set MOSI to SCLK delay 10 - - ns tMOSI-hold SCLK to MOSI delay 10 - - ns tMISO-delay SCLK to MISO delay, CL≤ 90 pF - - 30 ns tMISO-delay SCLK to MISO delay, CL = 25 pF (Design info) - - 21 ns tMISO-delay SCLK to MISO delay, CL = 200 pF (Design info) - - 75 ns tMISO-active CS to MISO active delay, CL≤ 90 pF - - 30 ns tMISO-tristate CS to MISO tristate delay, CL≤ 90 pF - - 30 ns tSPICS-high CS high time 200 - - ns IMISO_tristate MISO leakage current -10 - 10 µA Table 26. Direct interface Symbol Parameter / Condition Min Typ Max Unit VSYNCx-H SYNCx high threshold - - 2 V VSYNCx-L SYNCx low threshold 0.8 - - V ∆VSYNCx SYNCx Hysteresis 100 150 - mV tdeglitch Deglitch filter for SYNCx path - 500 - ns VDout-L DOUTx Low level (Isink=2mA) - - 0.4 V VDout-H DOUTx High level (Isource=2mA) VDD- 0.45 -- V tDOUTx-delay DOUTx output buffer delay, CL≤ 50pF (Design info) -- 90 ns - DOUTx rising and falling edge delay difference, CL≤ 50pF -50 - +50 ns tLatency_DOUTx_HF_IIR Latency time between receiving sensor data @ PSIx pin and reaching threshold high level of DOUTx pin (trigger point: 80% of PSIx modulated current, @189kBps, deglitch filter with default value). - - 3.05 µs |
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