L9663 datasheet(20/106 Pages) STMICROELECTRONICS

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Power supply

L9663

20/106

DS11401 Rev 6

circuit can be bypassed by disabling it through the dedicated SPI command (bit 12 of

CH1_CR2, CH2_CR2, writable during PROG phase).

The bootstrap blocks are automatically switched off in case the voltage on VB is high

enough to allow proper regulation. In this case both CBx capacitors should be omitted.

The VSYNCx voltage can supply a 2.5 V minimum sync pulse as per PSI5 v2.x low power

mode down to VB = 4.8 V and a 3.5 V minimum sync pulse down to VB = 5.2 V, with a

maximum quiescent current level of 35mA and down to minimum 200 µs period between

sync pulses. The block is protected against reverse feeding to VB.

The bootstrap module is fully functional while VB and VDD are all inside their specified

voltage ranges.

2.4

Power supply for PSI5 sensor line

Basic features:



Reverse voltage protection structure



Voltage limitation and current limitation for PSIx input/output



Protection against negative voltages on PSIx transceiver pin due to ground shifts



Disconnection of PSIx from VAS in failure cases

The PSI5 transceiver IC is supplied directly from the pin VAS. It includes blocks with the

following functionalities:



Reverse voltage protection structure and gate driver block for

–

Voltage clamp on PSIx in case of VAS fault

–

Backward voltage supply blocking mechanism from PSIx to VAS

–

Sensor supply by switching VAS to the PSIx pin

–

Disconnection of PSIx from the VAS if required or in failure cases



Under voltage detection block to implement cross coupling test between the two

channels (see Section 3.7.5 and 4.2)



Receiver block for Sensor Data receive (see Section 3.1 for details).

The reverse voltage protection structure is also used to switch off the PSIx transceiver

channel, if:



the local junction temperature exceeds its maximum rating and the channel is in

overcurrent



an overcurrent condition on PSIx is detected (STG)



a short to battery is detected



it is requested via SPI or RESETN pin.

In case of short to battery on the PSIx lines, there is no interference to any other IC

pin/supply including SPI.

The two interfaces can be enabled by SPI command, and the enable has effect only if VAS

under voltage signals are not asserted.

If an over temperature condition (OT) occurs, the interface that is also in overcurrent

condition is switched off and a failure bit is set. The fault bit is latched and cleared only when

a SPI switch off command is sent for confirmation on the line that was automatically

switched off. The shutoff of one interface does not affect the second interface.

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