L9663 datasheet(99/106 Pages) STMICROELECTRONICS

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DS11401 Rev 6

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L9663

Errata

105

Errata

Table 27. Errata

BugID#

Category /

Function

Issue Description

1526

Asynchronous

Mode

FIFO_LOCK could still stay set even after clearing of the data buffer

registers of the 2 PSI5 channels.

Assuming a low data rate from sensor compared to SPI readout, the

proposed workaround is to read both FIFOs in the following

sequence:

– Ch 1, slot 6

– Ch 2, slot 6

– Ch 1, slot 5

– Ch 2, slot 5

–…

– Ch 2, slot 1

Afterwards, if the FIFO_LOCK bit is still high, the following read

commands are needed:

– Ch 1, slot 1

– Ch 2, slot 1

1822

Sync Pulse

If the IC is configured to control the sync pulse length via pin

(PSIx_EXT_UDB=0 and PSIx_TRIG_SEL=00/11, x=1 or 2) the

generated sync pulse could be not compliant with the PSI5 standard,

depending on the trigger pulse duration tw.

– 1µs ≤ tw ≤ 5µs ≥ a short pulse is generated, PSI5 standard

compliant; ≥ Correct short pulse

– tw > 5µs ≥ the pulse could be not compliant with PSI5 standard,

two consecutive pulses could be generated instead of a single

pulse. ≥ Wrong pulse

1830

Cross coupling

test

XCTRSLT1/2 fault flags are swapped in master mode

3367

Clock monitor by

internal oscillator

The internal clock monitor (disabled by default) is not accurate

enough: fCLKERR_H/L thresholds overlap the main oscillator

operating range.

This function is disabled by default, it can be enabled by ST only

(burning a dedicated OTP bit).

If enabled it could detect false errors. => Activation is forbidden.

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