ST40RA datasheet(78/94 Pages) STMICROELECTRONICS

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ADCS 7260755H

STMicroelectronics

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ST40RA

A Interconnect architecture

Interconnect architecture

This detail is included for information only. It is not recommended to write to any of these registers,

without prior consultation from ST, as it could cause the device to malfunction.

ST only guarantees correct operation of the device with the default register values. The register

reset default values have been programmed to balance the system and give optimum system

performance, so there is no need to modify them.

For details of other registers see the

ST40 System Architecture Manual.

The internal architecture of the block is shown in

Figure 21.

Figure 21: ST40RA interconnect architecture

LMI

64-bit

full

cross bar

conn_2 x 2

EMI

EMPI

SH4 subsystem

subsystem

ST40 core

PER

sub

Node 2

CPU subsystem

Node 1

PCI

GPDMA

PCI

(t)

100 MHz

32-bit

conn_4 x 4

Full cross bar

Programming

port

Programming

port

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