ST40RA datasheet(60/94 Pages) STMICROELECTRONICS

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ADCS 7260755H

STMicroelectronics

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ST40RA

8 Pin description

MODE6

EADDR8

MD6

CLOCKGEN

Set enable CKIO

MODE7

EADDR9

MD7

EMISS

Enable MPX arbiter

MODE8

EADDR10

MD8

System

Set endianness

H: Little

L: Big

MODE9

EADDR11

MD9

EMI

Set EMI port

H: Master

L: Slave

MODE11:

EADDR12

EADDR13

MD11:10

EMI

Set booting ROM bus size

00: Reserved

01: 32-bit

10: 16-bit

11: 8-bit

MODE12

EADDR14

MD12

EMI

Enable NOP when accessing flash

MODE13

EADDR15

MD13

Reserved

Tie high

MODE14

EADDR16

MD14

PCI

PCI bridge mode

H: Host

L: Satellite

MODE15

EADDR17

MD15

PCI

Reserved: PCI select clock

H: External

L: Internal

MODE16

EADDR18

MD16

Reserved: Tie high

MODE17

EADDR19

MD17

MODE18

EADDR20

MD18

MODE19

EADDR21

MD19

a. See CLOCKGEN chapter of the

ST40 System Architecture Manual for details.

b. ST40RA is always the clock master, providing EMI clocks to the system.

c. See EMI chapter of the

ST40 System Architecture Manual for details.

d. reserved for enable retiming stage on EMI padlogic

e. PCI clock is selected externally on the board for ST40RA. The mode pin may be used for clock

selection in future variants.

f. These mode pins are not used in current variants, however, they may be used to enable additional

functionality in future variants

Mode

Pin name

Architectur

e signal

name

Block

affected

Description

Notes

Table 34: Mode selection pins for ST40RA

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