ST40RA datasheet(41/94 Pages) STMICROELECTRONICS

41 / 94 page

6 Clock generation

ST40RA

41/94

STMicroelectronics

ADCS 7260755H

6.6.3

CLOCKGENA.STBREQCR and CLOCKGENB.STBREQCR registers

6.6.4

CLOCKGENA.STBREQCR_SET and CLOCKGENB.STBREQCR_SET registers

6.6.5

CLOCKGENA.STBREQCR_CLR and CLOCKGENB.STBREQCR_CLR register

CLOCKGENA.STBREQCR

CLOCKGENB.STBREQCR

Control power down requests

0x0018

This register gives direct access to the power down request register. Low power requests are made in

the STBREQCR_SET register and cleared in the STBREQCR_CLR register.

[0:7]

REQ[0:7]

Power down requests for module [n]

Controls the power down state for module [n]

Bit [n]: 0 Request module [n] to operate normally

Bit [n]: 1 Request module [n] to power down

Reset state: 0

[8:31]

Reserved

0: No action

1: Undefined

Reset state: Undefined

CLOCKGENA.STBREQCR_SET

CLOCKGENB.STBREQCR_SET

Set power down requests

0x0020

This register sets a low power request.

[0:7]

SET[0:7]

Set power down request for module [n]

Sets the power down request state for module [n]

Bit [n]: 0 No action

Bit [n]: 1 Set power down request

Reset state: 0

[8:31]

Reserved

0: No action

1: Undefined

Reset state: Undefined

CLOCKGENA.STBREQCR_CLR

CLOCKGENB.STBREQCR_CLR

Clear power down requests

0x0028

This register clears a low power request and recommences the clock supply to a module.

[0:7]

CLR[0:7]

Clear power down request for module [n]

Clears the power down request state for module [n]

Bit [n]: 0 No action

Bit [n]: 1 Clear power down request

Reset state: 0

[8:31]

Reserved

0: No action

1: Undefined

Reset state: Undefined

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