AT80SND1C-ROTIL datasheet(37/210 Pages) ATMEL

37 / 210 page

AT8xC51SND1C

4109E–8051–06/03

Table 49. Priority Levels

A low-priority interrupt is always interrupted by a higher priority interrupt but not by

another interrupt of lower or equal priority. Higher priority interrupts are serviced before

lower priority interrupts. The response to simultaneous occurrence of equal priority inter-

rupts is determined by an internal hardware polling sequence detailed in Table 50.

Thus, within each priority level there is a second priority structure determined by the

polling sequence. The interrupt control system is shown in Figure 21.

Table 50. Priority within Same Level

IPHxx

IPLxx

Priority Level

0 Lowest

3 Highest

Interrupt Name

Priority Number

Interrupt Address

Vectors

Interrupt Request Flag

Cleared by Hardware

(H) or by Software (S)

INT0

1 (Highest Priority)

C:0003h

H if edge, S if level

Timer 0

C:000Bh

INT1

C:0013h

H if edge, S if level

Timer 1

C:001Bh

Serial Port

C:0023h

MP3 Decoder

C:002Bh

Audio Interface

C:0033h

MMC Interface

C:003Bh

Two Wire Controller

C:0043h

SPI Controller

C:004Bh

A to D Converter

C:0053h

Keyboard

C:005Bh

Reserved

C:0063h

USB

C:006Bh

Reserved

15 (Lowest Priority)

C:0073h

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