AT80SND1C-ROTIL datasheet(48/210 Pages) ATMEL

48 / 210 page

AT8xC51SND1C

4109E–8051–06/03

Entering Idle Mode

To enter Idle mode, the user must set the IDL bit in PCON register (see Table 59). The

AT8xC51SND1C enters Idle mode upon execution of the instruction that sets IDL bit.

The instruction that sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT8xC51SND1C enter Power-down

mode. Then it does not go in Idle mode when exiting Power-down mode.

Exiting Idle Mode

There are 2 ways to exit Idle mode:

Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Idle mode.

The general-purpose flags (GF1 and GF0 in PCON register) may be used to

indicate whether an interrupt occurred during normal operation or during Idle

mode. When Idle mode is exited by an interrupt, the interrupt service routine

may examine GF1 and GF0.

Generate a reset.

–

A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the

instruction that activated the Idle mode and may continue for a number of

clock cycles before the internal reset algorithm takes control. Reset

initializes the AT8xC51SND1C and vectors the CPU to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

Power-down Mode

The Power-down mode places the AT8xC51SND1C in a very low power state. Power-

down mode stops the oscillator and freezes all clocks at known states (refer to the Sec-

tion "Oscillator", page 12). The CPU status prior to entering Power-down mode is

preserved, i.e., the program counter, program status word register retain their data for

the duration of Power-down mode. In addition, the SFRs and RAM contents are pre-

served. The status of the Port pins during Power-down mode is detailed in Table 57.

Note:

DD may be reduced to as low as VRET during Power-down mode to further reduce power

dissipation. Notice, however, that VDD is not reduced until Power-down mode is invoked.

Entering Power-down Mode

To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND1C enters

the Power-down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

Exiting Power-down Mode

If V

DD was reduced during the Power-down mode, do not exit Power-down mode until

DD is restored to the normal operating level.

There are 2 ways to exit the Power-down mode:

Generate an enabled external interrupt.

–

The AT8xC51SND1C provides capability to exit from Power-down using

INT0, INT1, and KIN3:0 inputs. In addition, using KIN input provides high or

low level exit capability (see section “Keyboard Interface”, page 179).

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTn input, execution

AT80SND1C-ROTIL Datenblatt(PDF) 48 Page - ATMEL Corporation

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