R8C datasheet(46/199 Pages) RENESAS

46 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 36 of 180

REJ09B0019-0120

Interrupt factor

Vector addresses

Remarks

Reference

Address (L) to address (H)

Undefined instruction 0FFDC16 to 0FFDF16

Interrupt on UND instruction

R8C/Tiny series

Overflow

0FFE016 to 0FFE316

Interrupt on INTO instruction

software manual

BRK instruction

0FFE416 to 0FFE716

Address match

0FFE816 to 0FFEB16

10.4 Address match

interrupt

Single step(1)

0FFEC16 to 0FFEF16

Watchdog timer,

0FFF016 to 0FFF316

11.Watchdog timer,

oscillation stop

6. Clock generation

detection

circuit

(Reserved)

0FFF416 to 0FFF716

(Reserved)

0FFF816 to 0FFFB16

Reset

0FFFC16 to 0FFFF16

5. Reset

NOTES:

1. Do not normally use this interrupt because it is provided exclusively for use by development support tools.

Figure 10.2 Interrupt Vector

Mid address

Low address

0 0 0 0

High address

0 0 0 0

Vector address (L)

LSB

MSB

Vector address (H)

10.1.4 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec-

tive interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in

the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.

• Fixed Vector Tables

The fixed vector tables are allocated to the addresses from 0FFDC16 to 0FFFF16. Table 10.1

lists the fixed vector tables. In the flash memory version of microcomputer, the vector ad-

dresses (H) of fixed vectors are used by the ID code check function. For details, refer to Sec-

tion 17.3, “Functions to Prevent Flash Memory from Rewriting.”

Table 10.1 Fixed Vector Tables

If the contents of address

0FFE716 is FF16, program ex-

ecution starts from the address

shown by the vector in the

relocatable vector table.

10.1 Interrupt Overview

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