R8C datasheet(28/199 Pages) RENESAS

28 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 18 of 180

REJ09B0019-0120

CPU clock

Interrupt request level

judgment output

CM10=1(Stop mode)

WAIT instruction

On-chip

oscillator

clock

Main

clock

CM05

RESET

CM02

XOUT

XIN

fAD

f32

OCD2=0

OCD2=1

CM14

f8SIO

f32SIO

fRING

1/128

fRING128

f1SIO

CM02, CM05, CM06: Bits in CM0 register

CM10, CM13, CM14, CM16, CM17: Bits in CM1 register

OCD0, OCD1, OCD2: Bits in OCD register

Details of divider

1/2

CM06=0

CM17 to CM16=002

CM06=0

CM17 to CM16=012

CM06=0

CM17 to CM16=102

CM06=1

CM06=0

CM17 to CM16=112

1/2

Forcible discharge when OCD0(1)

OCD2 bit switch signal

OCD1(1)

CM14 bit switch signal

Pulse generation

circuit for clock

edge detection

and charge,

discharge control

circuit

Charge,

discharge

circuit

NOTES:

1. Set the same value to the OCD1 bit and OCD0 bit.

Oscillation stop

detection interrupt

generation circuit

Main clock

Watchdog

timer

interrupt

Oscillation stop

detection,

Watchdog timer

interrupt

Oscillation stop detection circuit

On-chip

oscillator

Oscillation

stop

detection

Divider

Peripheral

function clock

CM13

Figure 6.1 Clock Generation Circuit

6. Clock Generation Circuit

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