PIC18F44J10 datasheet(43/368 Pages) MICROCHIP

43 / 368 page

DS39682E-page 41

PIC18F45J10 FAMILY

5.0

RESET

The PIC18F45J10 family of devices differentiate

between various kinds of Reset:

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during power-managed modes

Watchdog Timer (WDT) Reset (during

execution)

Configuration Mismatch (CM)

Brown-out Reset (BOR)

RESET

Instruction

Stack Full Reset

Stack Underflow Reset

This section discusses Resets generated by MCLR,

POR and BOR and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 6.1.4.4 “Stack Full and Underflow Resets”

WDT Resets are covered in Section 21.2 “Watchdog

Timer (WDT)”

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 5-1.

5.1

RCON Register

Device Reset events are tracked through the RCON

indicate that a specific Reset event has occurred. In

most cases, these bits can only be set by the event and

must be cleared by the application after the event. The

state of these flag bits, taken together, can be read to

indicate the type of Reset that just occurred. This is

described in more detail in Section 5.7 “Reset State

of Registers”

The RCON register also has a control bit for setting

interrupt priority (IPEN). Interrupt priority is discussed

in Section 9.0 “Interrupts”.

FIGURE 5-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

WDT

Time-out

VDD Rise

Detect

PWRT

INTRC

POR Pulse

Chip_Reset

Brown-out

Reset(1)

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

( )_IDLE

μs

Note 1:

The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.

PWRT

11-Bit Ripple Counter

66 ms

Configuration Word Mismatch

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