PIC18F44J10 datasheet(49/368 Pages) MICROCHIP

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DS39682E-page 47

PIC18F45J10 FAMILY

TABLE 5-2:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets,

CM Resets

Wake-up via WDT

or Interrupt

TOSU

PIC18F2XJ10 PIC18F4XJ10

---0 0000

---0 uuuu(1)

TOSH

PIC18F2XJ10 PIC18F4XJ10

0000 0000

uuuu uuuu(1)

TOSL

PIC18F2XJ10 PIC18F4XJ10

0000 0000

uuuu uuuu(1)

STKPTR

PIC18F2XJ10 PIC18F4XJ10

00-0 0000

uu-0 0000

uu-u uuuu(1)

PCLATU

PIC18F2XJ10 PIC18F4XJ10

---0 0000

---u uuuu

PCLATH

PIC18F2XJ10 PIC18F4XJ10

0000 0000

uuuu uuuu

PCL

PIC18F2XJ10 PIC18F4XJ10

0000 0000

PC + 2(2)

TBLPTRU

PIC18F2XJ10 PIC18F4XJ10

--00 0000

--uu uuuu

TBLPTRH

PIC18F2XJ10 PIC18F4XJ10

0000 0000

uuuu uuuu

TBLPTRL

PIC18F2XJ10 PIC18F4XJ10

0000 0000

uuuu uuuu

TABLAT

PIC18F2XJ10 PIC18F4XJ10

0000 0000

uuuu uuuu

PRODH

PIC18F2XJ10 PIC18F4XJ10

xxxx xxxx

uuuu uuuu

PRODL

PIC18F2XJ10 PIC18F4XJ10

xxxx xxxx

uuuu uuuu

INTCON

PIC18F2XJ10 PIC18F4XJ10

0000 000x

0000 000u

uuuu uuuu(3)

INTCON2

PIC18F2XJ10 PIC18F4XJ10

1111 -1-1

uuuu -u-u(3)

INTCON3

PIC18F2XJ10 PIC18F4XJ10

11-0 0-00

uu-u u-uu(3)

INDF0

PIC18F2XJ10 PIC18F4XJ10

N/A

POSTINC0

PIC18F2XJ10 PIC18F4XJ10

N/A

POSTDEC0

PIC18F2XJ10 PIC18F4XJ10

N/A

PREINC0

PIC18F2XJ10 PIC18F4XJ10

N/A

PLUSW0

PIC18F2XJ10 PIC18F4XJ10

N/A

FSR0H

PIC18F2XJ10 PIC18F4XJ10

---- xxxx

---- uuuu

FSR0L

PIC18F2XJ10 PIC18F4XJ10

xxxx xxxx

uuuu uuuu

WREG

PIC18F2XJ10 PIC18F4XJ10

xxxx xxxx

uuuu uuuu

INDF1

PIC18F2XJ10 PIC18F4XJ10

N/A

POSTINC1

PIC18F2XJ10 PIC18F4XJ10

N/A

POSTDEC1

PIC18F2XJ10 PIC18F4XJ10

N/A

PREINC1

PIC18F2XJ10 PIC18F4XJ10

N/A

PLUSW1

PIC18F2XJ10 PIC18F4XJ10

N/A

FSR1H

PIC18F2XJ10 PIC18F4XJ10

---- xxxx

---- uuuu

FSR1L

PIC18F2XJ10 PIC18F4XJ10

xxxx xxxx

uuuu uuuu

BSR

PIC18F2XJ10 PIC18F4XJ10

---- 0000

---- uuuu

Legend: u

= unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

See Table 5-1 for Reset value for specific condition.

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