ATmega16 datasheet(73/357 Pages) ATMEL

73 / 357 page

2466S–AVR–05/09

ATmega16(L)

whether clk

T0 is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the Output Compare output

OC0. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 76.

The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare

Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the

Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1 and Global

Interrupt Flag in SREG is set), the Output Compare Flag generates an output compare interrupt.

The OCF0 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0

Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform gen-

erator uses the match signal to generate an output according to operating mode set by the

WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are

used by the waveform generator for handling the special cases of the extreme values in some

modes of operation (See “Modes of Operation” on page 76.).

Figure 29 shows a block diagram of the output compare unit.

Figure 29. Output Compare Unit, Block Diagram

The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

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