ATmega16 datasheet(98/357 Pages) ATMEL

98 / 357 page

2466S–AVR–05/09

ATmega16(L)

Output Compare

Units

The 16-bit comparator continuously compares TCNT1 with the Output Compare Register

(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output

Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-

pare Flag generates an output compare interrupt. The OCF1x Flag is automatically cleared

when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the Waveform Generation mode

(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals

are used by the Waveform Generator for handling the special cases of the extreme values in

some modes of operation (See “Modes of Operation” on page 101.)

A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the Waveform Generator.

Figure 43 shows a block diagram of the output compare unit. The small “n” in the register and bit

names indicates the device number (n = 1 for Timer/Counter1), and the “x” indicates output com-

pare unit (A/B). The elements of the block diagram that are not directly a part of the output

compare unit are gray shaded.

Figure 43. Output Compare Unit, Block Diagram

The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)

automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte

OCFnx (Int.Req.)

= (16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS (8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

COMnx1:0

WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit)

OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

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