ATmega16 datasheet(77/357 Pages) ATMEL

77 / 357 page

2466S–AVR–05/09

ATmega16(L)

the double buffering feature. If the new value written to OCR0 is lower than the current value of

TCNT0, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the

pin is set to output. The waveform generated will have a maximum frequency of f

OC0 = fclk_I/O/2

when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the compare

match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the

output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 32. The TCNT0 value is in the timing diagram shown as a histo-

gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare

matches between OCR0 and TCNT0.

Figure 32. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

fOCn

clk_I/O

OCRn

()

⋅⋅

-----------------------------------------------

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

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