ATmega328P datasheet(70/448 Pages) ATMEL

70 / 448 page

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

12. External Interrupts

The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins

are configured as outputs. This feature provides a way of generating a software interrupt. The

pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change

interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0

will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-

ters control which pins contribute to the pin change interrupts. Pin change interrupts on

PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for

waking the part also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is

set up as indicated in the specification for the External Interrupt Control Register A – EICRA.

When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-

rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge

interrupts on INT0 or INT1 requires the presence of an I/O clock, described in ”Clock Systems

and their Distribution” on page 26. Low level interrupt on INT0 and INT1 is detected asynchro-

nously. This implies that this interrupt can be used for waking the part also from sleep modes

other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in ”System Clock and Clock Options” on page 26.

12.1

Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 12-1.

Figure 12-1. Timing of pin change interrupts

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

PCIF

PCINT(0)

pin_sync

pcint_syn

pin_lat

pcint_setflag

PCIF

clk

PCINT(0) in PCMSK(x)

pcint_in_(0)

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