ATmega328P datasheet(77/448 Pages) ATMEL

77 / 448 page

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

13.2.2

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

13.2.3

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedance environment will not notice the difference between a strong high

driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to dis-

able all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

13.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 13-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 13-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t

pd,max and tpd,min respectively.

Table 13-1.

Port Pin Configurations

DDxn

PORTxn

PUD

(in MCUCR)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled low.

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

ATmega328P Datenblatt(PDF) 77 Page - ATMEL Corporation

ATmega328P Datenblatt(HTML) 77 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL