ATmega328P datasheet(45/448 Pages) ATMEL

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8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to

zero within four clock cycles.

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed

while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is

automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sleep Enable

BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable

is controlled by a timed sequence.

9.11.3

PRR – Power Reduction Register

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When

waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2

is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved in ATmega48PA/88PA/168PA/328P and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

If using debugWIRE On-chip Debug System, this bit should not be written to one.

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to

the module. When waking up the SPI again, the SPI should be re initialized to ensure proper

operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When

waking up the USART again, the USART should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

Bit

210

(0x64)

PRTWI

PRTIM2

PRTIM0

–

PRTIM1

PRSPI

PRUSART0

PRADC

PRR

Read/Write

R/W

Initial Value

ATmega328P Datenblatt(PDF) 45 Page - ATMEL Corporation

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