TMP320C6720RFP300 datasheet(87/118 Pages) TI

87 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-29. Additional(1) SPI Master Timings, 4-Pin Enable Option(2)(3)

NO.

MIN

MAX UNIT

Polarity = 0, Phase = 0,

3P + 15

to SPIx_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 3P + 15

Delay from slave assertion of

to SPIx_CLK rising

td(ENA_SPC)M

SPIx_ENA active to first

Polarity = 1, Phase = 0,

SPIx_CLK from master.(4)

3P + 15

to SPIx_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 3P + 15

to SPIx_CLK falling

Polarity = 0, Phase = 0,

0.5tc(SPC)M

from SPIx_CLK falling

Polarity = 0, Phase = 1,

Max delay for slave to deassert

from SPIx_CLK falling

SPIx_ENA after final SPIx_CLK

td(SPC_ENA)M

edge to ensure master does not

Polarity = 1, Phase = 0,

0.5tc(SPC)M

begin the next transfer.(5)

from SPIx_CLK rising

Polarity = 1, Phase = 1,

from SPIx_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes (Table 4-27).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPIx_ENA assertion.

(5)

In the case where the master SPI is ready with new data before SPIx_ENA deassertion.

Table 4-30. Additional(1) SPI Master Timings, 4-Pin Chip Select Option(2)(3)

NO.

MIN

MAX UNIT

Polarity = 0, Phase = 0,

2P – 10

to SPIx_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 2P – 10

to SPIx_CLK rising

Delay from SPIx_SCS active to

td(SCS_SPC)M

first SPIx_CLK(4)(5)

Polarity = 1, Phase = 0,

2P – 10

to SPIx_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 2P – 10

to SPIx_CLK falling

Polarity = 0, Phase = 0,

0.5tc(SPC)M

from SPIx_CLK falling

Polarity = 0, Phase = 1,

Delay from final SPIx_CLK edge

from SPIx_CLK falling

td(SPC_SCS)M

to master deasserting SPIx_SCS

Polarity = 1, Phase = 0,

(6) (7)

0.5tc(SPC)M

from SPIx_CLK rising

Polarity = 1, Phase = 1,

from SPIx_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes (Table 4-27).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPIx_SCS assertion.

(5)

This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(6)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain

asserted.

(7)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

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