TMP320C6720RFP300 datasheet(89/118 Pages) TI

89 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-32. Additional(1) SPI Slave Timings, 4-Pin Enable Option(2)(3)

NO.

MIN

MAX UNIT

Polarity = 0, Phase = 0,

P – 10

3P + 15

from SPIx_CLK falling

Polarity = 0, Phase = 1,

–0.5tc(SPC)M + P – 10

–0.5tc(SPC)M + 3P + 15

Delay from final

from SPIx_CLK falling

td(SPC_ENAH)S

SPIx_CLK edge to slave

Polarity = 1, Phase = 0,

deasserting SPIx_ENA.

P – 10

3P + 15

from SPIx_CLK rising

Polarity = 1, Phase = 1,

–0.5tc(SPC)M + P – 10

–0.5tc(SPC)M + 3P + 15

from SPIx_CLK rising

(1)

These parameters are in addition to the general timings for SPI slave modes (Table 4-28).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Table 4-33. Additional(1) SPI Slave Timings, 4-Pin Chip Select Option(2)(3)

NO.

MIN

MAX

UNIT

Required delay from SPIx_SCS asserted at slave to first

td(SCSL_SPC)S

SPIx_CLK edge at slave.

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P + 10

from SPIx_CLK falling

Polarity = 0, Phase = 1,

P + 10

Required delay from final

from SPIx_CLK falling

td(SPC_SCSH)S

SPIx_CLK edge before

Polarity = 1, Phase = 0,

SPIx_SCS is deasserted.

0.5tc(SPC)M + P + 10

from SPIx_CLK rising

Polarity = 1, Phase = 1,

P + 10

from SPIx_CLK rising

Delay from master asserting SPIx_SCS to slave driving

tena(SCSL_SOMI)S

P + 15

SPIx_SOMI valid

Delay from master deasserting SPIx_SCS to slave 3-stating

tdis(SCSH_SOMI)S

P + 15

SPIx_SOMI

(1)

These parameters are in addition to the general timings for SPI slave modes (Table 4-28).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

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