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IXP45X Datenblatt(PDF) 65 Page - Intel Corporation |
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IXP45X Datenblatt(HTML) 65 Page - Intel Corporation |
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65 / 148 page ![]() Package Information August 2006 Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet 65 Document Number: 306261-004US ETHC_COL Z VI VI VI I MII Mode of Operation: Asserted by the PHY when a collision is detected by the PHY. This MAC contains hardware hashing capabilities local to the interface. • When NPE C is configured in MII mode of operation and the signal is not being used, it should be pulled low through a 10-KΩ resistor. SMII Mode of Operation: Not used. • When NPE C is configured in SMII mode of operation, this signal must be pulled high through a 10-KΩ resistor. When this interface is disabled via the NPE-C Ethernet soft fuse (refer to the Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not being used a system design, this interface/signal is not required for any connection. ETHC_CRS Z VI VI VI I Asserted by the PHY when the transmit medium or receive medium are active. De-asserted when both the transmit and receive medium are idle. Remains asserted throughout the duration of collision condition. PHY asserts CRS asynchronously and de-asserts synchronously with respect to ETHC_RXCLK. This MAC contains hardware hashing capabilities local to the interface. Should be pulled high through a 10-KΩ resistor when not being utilized in the system or when in SMII mode of operation. Table 15. MII/SMII Interfaces (Sheet 7 of 7) Name Power on Reset† Reset† Normal After Reset Until Software Enables Possible Configur ations After Software Enables Type† Description Note: This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor, see Table 1 on page 13. † For a legend of the Type codes, see Table 8 on page 43. †† Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired |
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