IXP45X datasheet(63/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

ETH_MDIO

I/O

Management data output. Provides the write data to both PHY devices connected to each MII

interface. An external pull-up resistor of 1.5K ohm is required on ETH_MDIO to properly quantify

the external PHYs used in the system. For specific implementation, see the IEEE 802.3

specification.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

ETH_MDC

VI / VO

I/O

Management data clock. Management data interface clock is used to clock the MDIO signal as an

output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be

configured to be an output through an Intel API as documented in the Intel® IXP400 Software

Programmer’s Guide.

ETHC_TXCLK

Externally supplied transmit clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps operation

This MAC contains hardware hashing capabilities local to the interface.

This signal should be pulled high through a 10-KΩ resistor when being utilized in SMII mode of

operation.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

ETHC_TXDATA[3:1]

MII Mode of Operation:

Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This MAC

contains hardware hashing capabilities local to the interface.

SMII Mode of Operation:

Not used in SMII mode of operation.

ETHC_TXDATA[0] /

SMII_TXDATA[5]

MII Mode of Operation:

Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This MAC

contains hardware hashing capabilities local to the interface.

SMII Mode of Operation:

The data on this signal is transmitted synchronously with respect to the rising edge of SMII_CLK

when operating as an SMII interface and synchronously with respect to the rising edge of

SMII_TXCLK when operating as a Source Synchronous SMII interface

ETHC_TXEN

Indicates that the PHY is being presented with nibbles on the MII interface. Asserted

synchronously, with respect to ETHC_TXCLK, at the first nibble of the preamble, and remains

asserted until all the nibbles of a frame are presented. This MAC contains hardware hashing

capabilities local to the interface.

Table 15.

MII/SMII Interfaces (Sheet 5 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired

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