IXP45X datasheet(47/148 Pages) INTEL

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Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

PCI_PAR

I/O

PCI Parity used to check parity across the 32 bits of PCI_AD and the four bits of PCI_CBE_N.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_FRAME_N

I/O

PCI Cycle Frame used to signify the beginning and duration of a transaction. The signal will be

inactive prior to or during the final data phase of a given transaction.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_TRDY_N

I/O

PCI Target Ready informs that the target of the PCI bus is ready to complete the current data phase

of a given transaction.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_IRDY_N

I/O

PCI Initiator Ready informs the PCI bus that the initiator is ready to complete the transaction.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

PCI_STOP_N

I/O

PCI Stop indicates that the current target is requesting the current initiator to stop the current

transaction.

When this interface/signal is enabled and is not being used in a system design, the interface/signal

should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse

(refer to Expansion Bus Controller chapter of the Intel® IXP45X and Intel® IXP46X Product Line of

Network Processors Developer’s Manual) and is not being used in a system design, this interface/

signal is not required for any connection.

Table 11.

PCI Controller (Sheet 2 of 4)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

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