IXP45X datasheet(55/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

UTP_OP_FCI

UTOPIA Output data flow control input: Also known as the TXFULL/CLAV signal.

Used to inform the processor of the ability of each polled PHY to receive a complete cell. For cell-

level flow control in an MPHY environment, TxClav is an active high tri-stateable signal from the

MPHY to ATM layer. The UTP_OP_FCI, which is connected to multiple MPHY devices, will see logic

high generated by the PHY, one clock after the given PHY address is asserted — when a full cell

can be received by the PHY. The UTP_OP_FCI will see a logic low generated by the PHY one clock

cycle, after the PHY address is asserted — if a full cell cannot be received by the PHY.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA

and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel®

IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not

being used in a system design, this interface/signal is not required for any connection.

UTP_IP_CLK /

ETHA_RXCLK

ZVI

UTOPIA Mode of Operation:

UTOPIA Receive clock input. Also known as UTP_RX_CLK.

This signal is used to synchronize all UTOPIA-received inputs to the rising edge of the

UTP_IP_CLK.

MII Mode of Operation:

Externally supplied receive clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps operation

This MAC interface does not contain hardware hashing capabilities local to the interface.

SMII Mode of Operation:

Not used.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Table 14.

UTOPIA Level 2/MII_A/ SMII Interface (Sheet 3 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

For information on selecting the desired interface, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

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