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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

A signal called active high specifies that the interface is active when driven to a logic 1

and inactive when driven to a logic 0.

A signal called active low specifies that the interface is active when driven to a logic 0

and inactive when driven to a logic 1.

The following information attempts to explain how to interpret the tables. There are

five vertical columns:

• Power On Reset Active - This is when the Power on Reset signal is driven to logic 0.

When this happens the part will behave as described in this column irrelevant of the

settings on other signals.

• Reset Active - When Power on Reset is driven to a logic 1 and Reset is driven to a

logic 0, the part will exhibit this behavior.

• Normal After Reset Until Software Enables - This is sometimes called safe mode.

The intent of this is to allow the interface to be brought out of reset to a state,

which will not cause any protocol violations or any damage to the parts prior to

being enabled via software. This state will occur when both Power on Reset and

Reset are driven to a logic 1.

• Possible Configurations after Software Enables - This state describes the way that

the part is capable of behaving with appropriate software written. This state will

occur when both Power on Reset and Reset are driven to a logic 1.

Table 9.

Processors’ Signal Interface Summary Table

Reference

Table 10, “DDR SDRAM Interface” on page 45

Table 11, “PCI Controller” on page 46

Table 12, “High-Speed, Serial Interface 0” on page 50

Table 13, “High-Speed, Serial Interface 1” on page 51

Table 14, “UTOPIA Level 2/MII_A/ SMII Interface” on page 53

Table 15, “MII/SMII Interfaces” on page 59

Table 16, “Expansion Bus Interface” on page 66

Table 17, “UART Interfaces” on page 69

Table 18, “Serial Peripheral Port Interface” on page 70

Table 19, “I2C Interface” on page 70

Table 20, “USB Host/Device Interfaces” on page 71

Table 21, “Oscillator Interface” on page 72

Table 22, “GPIO Interface” on page 73

Table 23, “JTAG Interface” on page 73

Table 24, “System Interface” on page 74

Table 25, “Power Interface” on page 75

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