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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPEAR300 Datenblatt(PDF) 60 Page - STMicroelectronics |
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SPEAR300 Datenblatt(HTML) 60 Page - STMicroelectronics |
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60 / 83 page  Timing requirements SPEAr300 60/83 Doc ID 16324 Rev 2 MHz), setting BCD bit to '1', and the second one with the clock passing through a clock divider (83 MHz), setting BCD bit to '0'. 6.2.1 CLCD timing characteristics direct clock Figure 13. CLCD waveform with CLCP direct Figure 14. CLCD block diagram with CLCP direct Note: 1 tSTABLE = tCLOCK direct max - (tmax + tmin) 2For tmax the maximum value is taken from the worst case and best case, while for tmin the minimum value is taken from the worst case and best case. 3 CLCP should be delayed by {tmax + [tCLOCK direct max - (tmax + tmin)]/2} = 4.7915 ns Table 29. CLCD timings with CLCP direct Parameter Value Frequency tCLOCK direct max (tCLOCK ) 6 ns 166 MHz tCLOCK direct max rise (tr) 0.81 ns tCLOCK direct max (tf) 0.87 ns tmin -0.04 ns tmax 3.62 ns tSTABLE 2.34 ns Tmin Tmax CLCP CLD[23:0],CLAC,CLLE,CLLP, CLFP,CLPOWER Tclock Tr Tf Tstabl e Q Q SET CLR D t2 t3 CLCP CLD[23:0],CLAC,CLLE, CLLP,CLFP,CLPOWER CLCDCLK t1 |
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