SPEAR300 datasheet(64/83 Pages) STMICROELECTRONICS

64 / 83 page

Timing requirements

SPEAr300

64/83

Doc ID 16324 Rev 2

Note:

The timings shown in Figure 19 depend on the programmed value of TSCLHigh and TSCLLow,

so the values present in the three tables here above have been calculated using the

minimum programmable values of :

IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 registers (for High-Speed mode);

IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 registers (for Fast-Speed mode);

IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 registers (for Standard-Speed

mode).

Note:

These minimum values depend on the AHB clock (HCLK) frequency, which is 166 MHz.

A device may internally require a hold time of at least 300 ns for the SDA signal (referred to

the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL

(Please refer to the I2C Bus Specification v3-0 Jun 2007). However, the SDA data hold time

in the I2C controller of SPEAr300 is one-clock cycle based (6 ns with the HCLK clock at 166

MHz). This time may be insufficient for some slave devices. A few slave devices may not

receive the valid address due to the lack of SDA hold time and will not acknowledge even if

the address is valid. If the SDA data hold time is insufficient, an error may occur.

Workaround: If a device needs more SDA data hold time than one clock cycle, an RC delay

circuit is needed on the SDA line as illustrated in the following figure:

Figure 20.

RC delay circuit

For example, R= K and C = 200 pF.

6.4

FSMC timing characteristics

The characterization timing is done considering an output load of 3 pF on the data, 15 pF on

NF_CE, NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE.

The operating conditions are V= 0.90 V, T=125 °C in worst case and V=1.10 V, T= 40 °C in

best case.

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