74HC_HCT259

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Product data sheet

Rev. 5 — 7 August 2012

4 of 22

NXP Semiconductors

74HC259; 74HCT259

8-bit addressable latch

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;

q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.

Table 2.

Pin description

Symbol

Pin

Description

A0, A1, A2

1, 2, 3

address input

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

4, 5, 6, 7, 9, 10, 11, 12 latch output

GND

8

ground (0 V)

D

13

data input

LE

14

latch enable input (active LOW)

MR

15

conditional reset input (active LOW)

16

supply voltage

Table 3.

Function table[1]

Operating mode

Input

Output

MR

LE

D

A0

A1

A2

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Reset (clear)

L

H

X

X

X

X

LLLLLLLL

Demultiplexer

(active HIGH 8-channel)

decoder (when D = H)

L

L

d

L

L

L

Q = d LLLLLLL

L

L

d

H

L

L

LQ = d LLLLLL

L

L

d

L

H

L

LLQ = d LLLLL

L

L

d

H

H

L

LLLQ = d LLLL

L

L

d

L

L

H

LLLLQ = d LLL

L

L

d

H

L

H

LLLLLQ = d LL

L

L

d

L

H

H

LLLLLLQ = d L

L

L

d

H

H

H

LLLLLLLQ = d

Memory (no action)

H

H

X

X

X

X

Addressable latch

H

L

d

L

L

L

HL

d

HL

L

HL

d

L

HL

HL

d

HHL

H

Ld

LLH

HL

d

HL

H

HL

d

L

HH

HL

d

HHH

Q=d