1.

General description

The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC

standard No. 7-A.

The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for

general-purpose storage applications in digital systems. They are multifunctional devices

capable of storing single-line data in eight addressable latches. They provide a 3-to-8

decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also

incorporate an active LOW common reset (MR) for resetting all latches as well as an

active LOW enable input (LE).

The 74HC259; 74HCT259 has four modes of operation:

addressed latch. The addressed latch follows the data input with all non-addressed

latches remaining in their previous states.

unaffected by the data or address inputs.

the state of the data input (D) with all other outputs in the LOW state.

(A0 to A2) and data input (D).

When operating the 74HC259; 74HCT259 as an address latch, changing more than one

address bit could impose a transient wrong address. Therefore, this should only be done

while in the Memory mode.

2.

Features and benefits

74HC259; 74HCT259

8-bit addressable latch

Rev. 5 — 7 August 2012

Product data sheet