AD7938BCPZ datasheet(7/36 Pages) AD

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Data Sheet

AD7938/AD7939

Rev. C | Page 7 of 36

TIMING SPECIFICATIONS

VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to

TMAX, unless otherwise noted.

Table 4.

Limit at TMIN, TMAX

Parameter1

AD7938

AD7939

Unit

Description

fCLKIN2

700

kHz min

CLKIN frequency.

25.5

MHz max

tQUIET

ns min

Minimum time between end of read and start of next conversion; in other words, time

from when the data bus goes into three-state until the next falling edge of CONVST.

ns min

CONVST pulse width.

ns min

CONVST falling edge to CLKIN falling edge setup time.

ns max

CLKIN falling edge to BUSY rising edge.

ns min

CS to WR setup time.

ns min

CS to WR hold time.

ns min

WR pulse width.

ns min

Data setup time before WR.

ns min

Data hold after WR.

ns min

New data valid before falling edge of BUSY.

t10

ns min

CS to RD setup time.

t11

ns min

CS to RD hold time.

t12

ns min

RD pulse width.

t133

ns max

Data access time after RD.

t144

ns min

Bus relinquish time after RD.

ns max

Bus relinquish time after RD.

t15

ns min

HBEN to RD setup time.

t16

ns min

HBEN to RD hold time.

t17

ns min

Minimum time between reads/writes.

t18

ns min

HBEN to WR setup time.

t19

ns min

HBEN to WR hold time.

t20

ns max

CLKIN falling edge to BUSY falling edge.

t21

15.7

ns min

CLKIN low pulse width.

t22

7.8

ns min

CLKIN high pulse width.

Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of

1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).

Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.

The time required for the output to cross 0.4 V or 2.4 V.

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the

bus loading.

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