AD7938BCPZ datasheet(30/36 Pages) AD

30 / 36 page

AD7938/AD7939

Data Sheet

Rev. C | Page 30 of 36

AD7938/AD7939 to ADSP-21065L Interface

Figure 44 shows a typical interface between the

AD7938/AD7939 and the ADSP-21065L SHARC® processor.

This interface is an example of one of three DMA handshake

modes. The MSX control line is actually three memory select

lines. Internal ADDR25-24are decoded into MS3to0, and these

lines are then asserted as chip selects. The DMAR1 (DMA

request 1) is used in this setup as the interrupt to signal the end

of conversion. The rest of the interface is a standard

handshaking operation.

AD7938/

AD7939*

ADSP-21065L*

DB0 TO DB11

D0 TO D31

ADDR0 TO ADDR23

MSX

DMAR1

BUSY

CONVST

DSP/USER SYSTEM

*ADDITIONAL PINS OMITTED FOR CLARITY.

ADDRESS BUS

DATA BUS

ADDRESS

LATCH

ADDRESS

DECODER

Figure 44. Interfacing to the ADSP-21065L

AD7938/AD7939 to TMS32020, TMS320C25, and

TMS320C5x Interface

Parallel interfaces between the AD7938/AD7939 and the

TMS32020, TMS320C25, and TMS320C5x family of DSPs are

shown in Figure 45. The memory mapped address chosen for

the AD7938/AD7939 should be chosen to fall in the I/O

memory space of the DSPs. The parallel interface on the

AD7938/AD7939 is fast enough to interface to the TMS32020

with no extra wait states. If high speed glue logic, such as 74AS

devices, is used to drive the RD and the WR lines when

interfacing to the TMS320C25, no wait states are necessary.

However, if slower logic is used, data accesses can be slowed

sufficiently when reading from, and writing to, the part to

require the insertion of one wait state. Extra wait states are

necessary when using the TMS320C5x at their fastest clock

speeds (see the TMS320C5x User’s Guide for details).

Data is read from the ADC using the following instruction

IN D, ADC

where:

D is the data memory address.

ADC is the AD7938/AD7939 address.

AD7938/

AD7939*

TMS32020/

TMS320C25/

TMS320C50*

DB11 TO DB0

DMD0 TO DMD15

A0 TO A15

READY

INTX

BUSY

CONVST

DSP/USER SYSTEM

TMS320C25

ONLY

R/W

STRB

*ADDITIONAL PINS OMITTED FOR CLARITY.

ADDRESS BUS

DATA BUS

ADDRESS

DECODER

MSC

Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x

AD7938/AD7939 to 80C186 Interface

Figure 46 shows the AD7938/AD7939 interfaced to the 80C186

microprocessor. The 80C186 DMA controller provides two

independent high speed DMA channels where data transfer can

occur between memory and I/O spaces. Each data transfer

consumes two bus cycles, one cycle to fetch data and the other

to store data. After the AD7938/AD7939 finish a conversion,

the BUSY line generates a DMA request to Channel 1 (DRQ1).

Because of the interrupt, the processor performs a DMA read

operation that also resets the interrupt latch. Sufficient priority

must be assigned to the DMA channel to ensure that the DMA

request is serviced before the completion of the next conversion.

AD7938/

AD7939*

80C186*

DB0 TO DB11

AD0 TO AD15

A16 TO A19

ALE

DRQ1

BUSY

CONVST

MICROPROCESSOR/

USER SYSTEM

*ADDITIONAL PINS OMITTED FOR CLARITY.

ADDRESS/DATA BUS

ADDRESS BUS

DATA BUS

ADDRESS

LATCH

ADDRESS

DECODER

Figure 46. Interfacing to the 80C186

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