AD7938/AD7939

Data Sheet

Rev. C | Page 16 of 36

SEQUENCER OPERATION

The configuration of the SEQ and SHDW bits in the control

register allows the user to select a particular mode of operation

of the sequencer function. Table 11 outlines the four modes of

operation of the sequencer.

Writing to the Control Register to Program the Sequencer

The AD7938/AD7939 need 13 full CLKIN periods to perform a

conversion. If the ADC does not receive the full 13 CLKIN

periods, the conversion aborts. If a conversion is aborted after

applying 12.5 CLKIN periods to the ADC, ensure that a rising

edge of CONVST or a falling edge of CLKIN is applied to the

part before writing to the control register to program the

sequencer. If these conditions are not met, the sequencer will

not be in the correct state to handle being reprogrammed for

another sequence of conversions and the performance of the

converter is not guaranteed.

Table 10. Analog Input Type Selection

Channel Address

MODE0 = 0, MODE1 = 0

MODE0 = 0, MODE1 = 1

MODE0 = 1, MODE1 = 0

MODE0 = 1, MODE1 = 1

Eight Single-Ended

Input Channels

Four Fully Differential

Input Channels

Four Pseudo Differential Input

Channels (Pseudo Mode 1)

Seven Pseudo Differential Input

Channels (Pseudo Mode 2)

ADD2

ADD1

ADD0

0

0

0

AGND

0

0

1

AGND

0

1

0

AGND

0

1

1

AGND

1

0

0

AGND

1

0

1

AGND

1

1

0

AGND

1

1

1

AGND

Not Allowed

Table 11. Sequence Selection

SEQ

SHDW

Sequence Type

0

0

This configuration is selected when the sequence function is not used. The analog input channel selected on each

individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write

operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function

being used, where each write to the AD7938/AD7939 selects the next channel for conversion.

0

1

This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to

DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST

falling edge. See the Shadow Register section and Table 12.

1

0

If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write

operation. This allows other bits in the control register to be altered between conversions while in a sequence without

terminating the cycle.

1

1

This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous

conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by

the channel address bits in the control register.