AD7938BCPZ datasheet(23/36 Pages) AD

23 / 36 page

Data Sheet

AD7938/AD7939

Rev. C | Page 23 of 36

Using the Sequencer: Programmable Sequence

(SEQ = 0, SHDW = 1)

The AD7938/AD7939 can be configured to automatically cycle

through a number of selected channels using the on-chip

programmable sequencer by setting SEQ = 0 and SHDW = 1 in

the control register. The analog input channels to be converted

are selected by setting the relevant bits in the shadow register

to 1 (see Table 12).

Once the shadow register has been programmed with the

required sequence, the next conversion executed is on the

lowest channel programmed in the SHDW register. The next

conversion executed is on the next highest channel in the

sequence and so on. When the last channel in the sequence

is converted, the internal multiplexer returns to the first

channel selected in the shadow register and commences the

sequence again.

It is not necessary to write to the control register again once a

sequencer operation has been initiated. The WR input must be

kept high to ensure that the control register is not accidentally

overwritten or that a sequence operation is not interrupted. If

the control register is written to at any time during the sequence,

ensure that the SEQ and SHDW bits are set to 1, 0 to avoid

interrupting the conversion sequence. The sequence program

remains in force until such time as the AD7938/AD7939 is

written to and the SEQ and SHDW bits are configured with any

bit combination except 1, 0. Figure 32 shows a flow chart of the

programmable sequence operation.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION

SET SEQ = 0 SHDW = 1.

INITIATE A WRITE CYCLE.

THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER.

SET RELEVANT BITS TO SELECT

THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.

SEQ BIT = 1

SHDW BIT = 0

CONTINUOUSLY CONVERT

CONSECUTIVE

CHANNELS SELECTED

WITH EACH CONVST PULSE

BUT ALLOWS THE RANGE,

CODING, ANALOG INPUT TYPE,

ETC BITS IN THE CONTROL

WITHOUT INTERRUPTING

THE SEQUENCE.

CONTINUOUSLY CONVERT

CONSECUTIVE

CHANNELS SELECTED

IN THE SHADOW REGISTER

WITH EACH CONVST PULSE.

WR = HIGH

SEQ BIT = 0

SHDW BIT = 1

Figure 32. Programmable Sequence Flow Chart

Consecutive Sequence (SEQ = 1, SHDW = 1)

A sequence of consecutive channels can be converted beginning

with Channel 0 and ending with a final channel selected by

writing to the ADD2 to ADD0 bits in the control register. This

is done by setting the SEQ and SHDW bits in the control

having to write to the shadow register. To set this mode up, the

next conversion, once the control register is written to, is on

Channel 0, then Channel 1, and so on, until the channel

selected by the address bits (ADD2 to ADD0) is reached. The

cycle begins again provided the WR input is tied high. If low,

the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to

continue its preprogrammed sequence uninterrupted. Figure 33

shows the flowchart of the consecutive sequence mode.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION SELECT

FINAL CHANNEL (ADD2 TO ADD0) IN

CONSECUTIVE SEQUENCE.

SET SEQ = 1 SHDW = 1.

CONTINUOUSLY CONVERT A CONSECUTIVE

SEQUENCE OF CHANNELS FROM CHANNEL 0

UP TO AND INCLUDING THE PREVIOUSLY

SELECTED FINAL CHANNEL ON ADD2 TO ADD0

WITH EACH CONVST PULSE.

SEQ BIT = 1

SHDW BIT = 0

CONTINUOUSLY CONVERT

CONSECUTIVE CHANNELS SELECTED

WITH EACH CONVST PULSE BUT

ALLOWS THE RANGE, CODING, ANALOG

INPUT TYPE, ETC. BITS IN THE

CONTROL REGISTER TO BE CHANGED

WITHOUT INTERRUPTING

THE SEQUENCE.

Figure 33. Consecutive Sequence Mode Flow Chart

REFERENCE

The AD7938/AD7939 can operate with either the on-chip

reference or external reference. The internal reference is

selected by setting the REF bit in the internal control register

to 1. A block diagram of the internal reference circuitry is

shown in Figure 34. The internal reference circuitry includes an

on-chip 2.5 V band gap reference and a reference buffer. When

using the internal reference, the VREFIN/VREFOUT pin should be

decoupled to AGND with a 0.47 μF capacitor. This internal

reference not only provides the reference for the analog-to-

digital conversion, but it can also be used externally in the

system. It is recommended that the reference output is buffered

using an external precision op amp before applying it anywhere

in the system.

REFERENCE

AD7938/

AD7939

ADC

BUFFER

VREFIN/

VREFOUT

Figure 34. Internal Reference Circuit Block Diagram

AD7938BCPZ Datenblatt(PDF) 23 Page - Analog Devices

AD7938BCPZ Datenblatt(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datenblatt Download

Link URL