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NVT2004TL Datenblatt(PDF) 7 Page - NXP Semiconductors |
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NVT2004TL Datenblatt(HTML) 7 Page - NXP Semiconductors |
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7 / 33 page ![]() NVT2003_04_06 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 February 2014 7 of 33 NXP Semiconductors NVT2003/04/06 Bidirectional voltage-level translator (1) In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(A) should be such that Vref(B) is at least 1 V higher than Vref(A) for best translator operation. (2) Note that the enable time and the disable time are essentially controlled by the RC time constant of the capacitor and the 200 k resistor on the EN pin. Fig 8. Typical application circuit (switch enable control) Fig 9. Bidirectional translation to multiple higher voltage levels 002aae135 A1 A2 VREFA GND 3 4 VREFB 1 6 5 B1 B2 8EN SW SW NVT2002 7 200 k Ω RPU RPU Vpu(D) = 3.3 V I2C-BUS DEVICE SCL SDA VCC GND 2 Vref(A) = 1.8 V(1) RPU RPU I2C-BUS MASTER SCL SDA VCC GND on off 3.3 V enable signal(1) (2) EN VREFB 002aae133 B1 B2 200 k Ω CHIPSET I/O VCC 5 V totem pole or open-drain I/O GND VREFA A1 A2 B3 VCC Bn 3.3 V A3 An CPU I/O VCORE 1.8 V 1.5 V 1.2 V 1.0 V SW NVT20XX SW SW CHIPSET I/O SW B4 A4 B5 A5 SW SW B6 A6 SW |
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