NVT2004TL datasheet(12/33 Pages) PHILIPS

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NVT2003_04_06

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Product data sheet

Rev. 5 — 19 February 2014

12 of 33

NXP Semiconductors

NVT2003/04/06

Bidirectional voltage-level translator

capacitance. As the level moves below the VCC(A) voltage, the channel resistance drops

so that both A and B sides equal. The capacitance on both sides is connected to form the

total capacitance and the pull-up resistors on both sides combine to the parallel equivalent

resistance. The Ron of the device is small compared to the pull-up resistor values, so its

effect on the pull-up resistance can be neglected and the fall is determined by the driver

pulling the combined capacitance and pull-up resistor currents. An estimation of the actual

fall time seen by the device is equal to the time it takes for the B-side to fall to the VCC(A)

voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level.

A description of the rise time applied to either An or Bn output going from LOW to HIGH is

as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B sides

are essentially one node. They will rise together with an RC time constant that is the sum

of all the capacitance from both sides and the parallel of the resistance from both sides.

As the signal approaches the VCC(A) voltage, the channel resistance goes up and the

waveforms separate, with the B side finishing its rise with the RC time constant of the

B side. The rise to VCC(A) is essentially the same for both sides.

There are some basic guidelines to follow that will help maximize the performance of the

device:

• Keep trace length to a minimum by placing the NVT device close to the processor.

• The signal round trip time on trace should be shorter than the rise or fall time of signal

to reduce reflections.

• The faster the edge of the signal, the higher the chance for ringing.

• The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher

the frequency the device can use.

The system designer must design the pull-up resistor value based on external current

drive strength and limit the node capacitance (minimize the wire, stub, connector and

trace length) to get the desired operation frequency result.

Limiting values

[1]

The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp

current ratings are observed.

[2]

Low duty cycle pulses, not DC because of heating.

Table 9.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Over operating free-air temperature range.

Symbol

Parameter

Conditions

Min

Max

Unit

Vref(A)

reference voltage (A)

0.5

Vref(B)

reference voltage (B)

0.5

input voltage

0.5[1]

VI/O

voltage on an input/output pin

0.5[1]

Ich

channel current (DC)

128

IIK

input clamping current

VI <0V

50

IOK

output clamping current

[2]

50

+50

Tstg

storage temperature

65

+150

C

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