NVT2004TL datasheet(16/33 Pages) PHILIPS

16 / 33 page

NVT2003_04_06

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 19 February 2014

16 of 33

NXP Semiconductors

NVT2003/04/06

Bidirectional voltage-level translator

12. Performance curves

tPLH up-translation is typically dominated by the RC time constant, i.e.,

CL(tot)  RPU =50pF  197  = 9.85 ns, but the Ron  CL(tot) =50pF  5  =0.250 ns.

tPHL is typically dominated by the external pull-down driver + Ron, which is typically small

compared to the tPLH in an up-translation case.

Enable/disable times are dominated by the RC time constant on the EN pin since the

transistor turn off is on the order of ns, but the enable RC is on the order of ms.

Fall time is dominated by the external pull-down driver with only a slight Ron addition.

Rise time is dominated by the RPU  CL.

Skew time within the part is virtually non-existent, dominated by the difference in bond

wire lengths, which is typically small compared to the board-level routing differences.

Maximum data rate is dominated by the system capacitance and pull-up resistors.

(1) VI(EN) = 1.5 V; IO =64mA; VI =0V.

(2) VI(EN) = 4.5 V; IO =15mA; VI =2.4 V.

(3) VI(EN) = 2.3 V; IO =64mA; VI =0V.

(4) VI(EN) = 3.0 V; IO =64mA; VI =0V.

(5) VI(EN) = 4.5 V; IO =64mA; VI =0V.

(1) VI(EN) = 3.0 V; IO =15 mA; VI =2.4 V.

(2) VI(EN) = 2.3 V; IO =15 mA; VI =1.7 V.

Fig 16. NVT2006 typical capacitance versus propagation delay

0.2

0.4

0.6

tPD

(ns)

C (pF)

100

002aaf707

(1)

(2)

(3)

(4)

(5)

tPD

(ns)

C (pF)

100

002aaf708

(1)

(2)

NVT2004TL Datenblatt(PDF) 16 Page - NXP Semiconductors

NVT2004TL Datenblatt(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datenblatt Download

Link URL