NVT2003_04_06

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Product data sheet

Rev. 5 — 19 February 2014

11 of 33

NXP Semiconductors

NVT2003/04/06

Bidirectional voltage-level translator

7.5 How to design for maximum frequency operation

The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as

rise time and fall time. See Equation 1 as an example of the maximum frequency. The rise

and fall times are shown in Figure 11.

(1)

The rise and fall times are dependent upon translation voltages, the drive strength, the

The node capacitance is the addition of the PCB trace capacitance and the device

capacitance that exists on the bus. Because of the dependency of the external

components, PCB layout and the different device operating states the calculation of rise

and fall times is complex and has several inflection points along the curve.

The main component of the rise and fall times is the RC time constant of the bus line when

the device is in its two primary operating states: when device is in the ON state and it is

low-impedance, the other is when the device is OFF isolating the A-side from the B-side.

A description of the fall time applied to either An or Bn output going from HIGH to LOW is

voltage. The time is determined by the pull-up resistor, pull-down driver strength and the

Table 8.

Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx

A-side

B-side

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

5.0 V

1.0 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

Fig 11. An example waveform for maximum frequency

f

max

1

t

LOW min



t

HIGH min



t

r actual



t

f actual



++

+

-------------------------------------------------------------------------------------------------------------

=

002aag912

GND