LM5037MTSLASHNOPB datasheet(28/40 Pages) TI

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DEAD

OSC

RT1

175

300

19.5 k

0.162

DEAD

RT2

175

35 k

LM5037

SNVS578D – NOVEMBER 2008 – REVISED MAY 2015

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8.2.1 Design Requirements

•

Operating input voltage range: 36 V to 72 V

•

Output voltage: 5 V

•

Output current: 10 A

•

UVLO On Level: 34 V On (rising)

•

UVLO Off Level: 30 V Off (falling)

•

Output ripple voltage, VRIPPLE(OUT): < 2% (960 mVP-P)

•

Oscillator frequency ( 2× fSW per phase): 300 kHz

•

Switching frequency ( fSW per phase): 150 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Oscillator Frequency and Maximum Duty Cycle

The LM5037 oscillator frequency is twice the switching frequency of each switch in the half-bridge power stage.

fOSC = 2 × fSW

(13)

Calculate the dead-time resistor value for RRT2. The recommended of dead-time range is between 50 ns and 250

ns. A value of 175 ns is chosen, which sets a maximum duty cycle of approximately 95%. Equation 14 calculates

the RRT2 resistor value, (R9 in Figure 27) .

(14)

Use the nearest standard E96 value of 34.8 k

Ω.

Use the resistor value on the RT2 pin to calculate the required resistor value for the RT1 pin (R8 in Figure 27)

using Equation 15.

(15)

Use the nearest E96 value of 20 k

Ω.

8.2.2.2 Power Stage Design

As shown in the schematic in Figure 27, the primary components of the half-bridge power stage are:

•

Half-bridge splitter capacitors (C1, C2, C3, C4, C5 and C6)

•

Power MOSFETs (Q1 and Q2)

•

Power transformer (T1)

•

Output rectifier (D3)

•

Output filter (L2 and C18, C19, and C20)

The half-bridge stage DC input voltage divides evenly across the splitter capacitors, so that one end of the

primary-side of the power transformer connects to a DC level of approximately VIN/2. The other end of the

transformer primary is alternately connected by Q1 to the VIN pin, and then by Q2 to GND, with appropriate

dead-time in between. The device modulates the dead-time or duty cycle in order to regulate the output voltage

to the required level. Thus the primary winding is subjected to a bi-polar voltage swing of ±VIN/2. This voltage is

then scaled by the secondary to primary turns ratio (NS/NP). The secondary winding is center-tapped, so that the

double-diode, D3 can then full-wave rectify the bi-polar secondary waveform. A uni-polar pulse train occurs at the

full fOSC frequency of 300 kHz at the cathode of D3. Output filter inductor L2 and output capacitors C18, C19,

C20 then filter this pulse train to a DC output voltage plus AC ripple at the fOSC frequency.

The PWM controller adjusts the duty cycle with input line voltage in order to regulate the output voltage. The

maximum duty cycle occurs at minimum operating input voltage, which is approximately 30 V (UVLO turn-off

point).

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