MCP3910A1T-ESLASHML datasheet(20/86 Pages) MICROCHIP

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MCP3910

DS20005116B-page 20

 2012-2014 Microchip Technology Inc.

3.2

Digital VDD (DVDD)

DVDD is the power supply voltage for the digital circuitry

within the MCP3910. For optimal performance, it is rec-

ommended to connect appropriate bypass capacitors

(typically a 10 µF in parallel with a 0.1 µF ceramic).

DVDD should be maintained between 2.7V and 3.6V for

specified operation.

3.3

Analog VDD (AVDD)

AVDD is the power supply voltage for the analog cir-

cuitry within the MCP3910. For optimal performance, it

is recommended to connect appropriate bypass capac-

itors (typically a 10 µF in parallel with a 0.1 µF

ceramic). AVDD should be maintained between 2.7V

and 3.6V for specified operation.

3.4

ADC Differential Analog Inputs

(CHn+/CHn-)

The CHn+/- pins (n comprised between 0 and 1) are

the two fully differential analog voltage inputs for the

Delta-Sigma ADCs.

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mV/GAIN with

VREF = 1.2V.

The maximum absolute voltage, with respect to AGND,

for each CHn+/- input pin is ±1V with no distortion and

±2V with no breaking after continuous voltage. This

maximum absolute voltage is not proportional to the

VREF voltage.

3.5

Analog Ground (AGND)

AGND is the ground reference voltage for the analog

circuitry within the MCP3910. For optimal performance,

it is recommended to connect it to the same ground

node voltage as DGND, again preferable with a star

connection.

If an analog ground plane is available, it is

recommended that these pins be tied to this plane of

the PCB. This plane should also reference all other

analog circuitry in the system.

3.6

Non-Inverting Reference Input,

Internal Reference Output

(REFIN+/OUT)

This pin is the non-inverting side of the differential

voltage reference input for all ADCs or the internal

voltage reference output.

When VREFEXT = 1, an external voltage reference

source can be used, and the internal voltage reference

is disabled. When using an external differential voltage

reference, it should be connected to its VREF+ pin.

When using an external single-ended reference, it

should be connected to this pin.

When VREFEXT = 0, the internal voltage reference is

enabled and connected to this pin through a switch.

This voltage reference has minimal drive capability and

thus needs proper buffering and bypass capacitances

(a 0.1 µF ceramic capacitor is sufficient in most cases),

if used as a voltage source.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not necessary for keeping ADC accuracy, but a minimal

0.1 µF ceramic capacitance can be connected to avoid

EMI/EMC susceptibility issues due to the antenna

created by the REFIN+/OUT pin if left floating.

3.7

Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage

reference input for all ADCs. When using an external

differential voltage reference, it should be connected to

its VREF- pin. When using an external single-ended

voltage reference, or when VREFEXT = 0 (default) and

using the internal voltage reference, the pin should be

directly connected to AGND.

3.8

Digital Ground Connection (DGND)

DGND is the ground reference voltage for the digital

circuitry within the MCP3910. For optimal performance,

it is recommended to connect it to the same ground

node voltage as AGND, again preferable with a star

connection.

If a digital ground plane is available, it is recommended

that these pins be tied to this plane of the Printed Circuit

Board (PCB). This plane should also reference all other

digital circuitry in the system.

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