MCP3910A1T-ESLASHML datasheet(40/86 Pages) MICROCHIP

40 / 86 page

MCP3910

DS20005116B-page 40

 2012-2014 Microchip Technology Inc.

The Phase delay registers can be programmed once

with the OSR = 4096 setting, and will adjust the OSR

automatically afterward without the need to change the

value of the phase registers.

• OSR = 4096

: The delay can go from -2048 to

+2047. PHASE<11> is the sign bit. PHASE<10>

is the MSB and PHASE<0> the LSB.

• OSR = 2048

: The delay can go from -1024 to

+1023. PHASE<10> is the sign bit. PHASE<9> is

the MSB and PHASE<0> the LSB.

• OSR = 1024

: The delay can go from -512 to +511.

PHASE<9> is the sign bit. PHASE<8> is the MSB

and PHASE<0> the LSB.

• OSR = 512

: The delay can go from -256 to +255

PHASE<8> is the sign bit. PHASE<7> is the MSB

and PHASE<0> the LSB.

• OSR = 256: The delay can go from -128 to +127.

PHASE<7> is the sign bit. PHASE<6> is the MSB

and PHASE<0> the LSB.

• OSR = 128: The delay can go from -64 to +63.

PHASE<6> is the sign bit. PHASE<5> is the MSB

and PHASE<0> the LSB.

• OSR = 64: The delay can go from -32 to +31.

PHASE<5> is the sign bit. PHASE<4> is the MSB

and PHASE<0> the LSB.

• OSR = 32: The delay can go from -16 to +15.

PHASE<4> is the sign bit. PHASE<3> is the MSB

and PHASE<0> the LSB.

5.10

Crystal Oscillator

The MCP3910 includes a Pierce-type crystal oscillator

with very high stability and ensures very low tempco

and jitter for the clock generation. This oscillator can

handle crystal frequencies up to 20 MHz provided that

proper load capacitances and quartz quality factor are

used. The crystal oscillator is enabled when

CLKEXT = 0 in the CONFIG1 register, therefore it can-

not be enabled during the 2-Wire Interface mode. It is

only selectable in the SPI Mode.

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND and

between OSC2 and DGND. They should also respect

Equation 5-7.

EQUATION 5-7:

When CLKEXT = 1, the crystal oscillator is bypassed

by a digital buffer, to allow direct clock input for an

external clock (see Figure 4-1). In this case, OSC2

becomes the MODE select input pin for the Interface

mode. When MODE = 0, the digital interface stays in

SPI mode; when MODE = 1, the digital interface

toggles to the 2-Wire mode. A pull-down current forces

the MODE to be logic low (SPI mode) by default if the

OSC2 pin is floating.

The external clock should not be higher than 20 MHz

before

prescaling

(MCLK < 20 MHz)

for

proper

operation.

TABLE 5-9:

PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 4096,

PRE<1:0> = 00

PHASE<11:0>

Hex

Delay

(CH0 relative

to CH1)

0111 111111 11

0x7FF

+ 2047 µs

0111 111111 10

0x7FE

+ 2046 µs

0000 000000 01

0x001

+ 1 µs

0000 000000 00

0x000

0 µs

1111 111111 11

0xFFF

- 1 µs

1000 000000 01

0x801

- 2047 µs

1000 000000 00

0x800

-2048 µs

Note:

In addition to the conditions defining the

maximum MCLK input frequency range,

the

AMCLK

frequency

should

maintained inferior to the maximum limits

defined in Table 5-2, to ensure the

accuracy of the ADCs. If these limits are

exceeded, it is recommended to choose

either a larger OSR, or a larger prescaler

value so that AMCLK can respect these

limits.

1.6



LOAD

-------------------------







Where:

f = crystal frequency in MHz

CLOAD = load capacitance in pF including

parasitics from the PCB

RM = motional resistance of the quartz, in

ohms

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